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1 16-megabit 2.7-volt only serial dataflash ? AT45DB161 features ? single 2.7v - 3.6v supply serial interface architecture page program operation ? single cycle reprogram (erase and program) ? 4096 pages (528 bytes/page) main memory optional page and block erase operations two 528-byte sram data buffers ? allows receiving of data while reprogramming of nonvolatile memory internal program and control timer fast page program time ? 7 ms typical 120 s typical page to buffer transfer time low power dissipation ? 4 ma active read current typical ? 3 a cmos standby current typical 13 mhz max clock frequency hardware data protection feature serial peripheral interface (spi) compatible ? modes 0 and 3 cmos and ttl compatible inputs and outputs commercial and industrial temperature ranges description the AT45DB161 is a 2.7-volt only, serial interface flash memory suitable for in-system reprogramming. its 17,301,504 bits of memory are organized as 4096 pages of 528 bytes each. in addition to the main memory, the AT45DB161 also con- tains two sram data buffers of 528 bytes each. the buffers allow receiving of data rev. 0807d?08/00 pin configurations pin name function cs chip select sck serial clock si serial input so serial output wp hardware page write protect pin reset chip reset rdy/busy ready/busy (continued) tsop top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rdy/busy reset wp nc nc vcc gnd nc nc nc cs sck si so nc nc nc nc nc nc nc nc nc nc nc nc nc nc plcc 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 sck si so nc nc nc nc nc nc wp reset rdy/busy nc nc nc nc nc nc 4 3 2 1 32 31 30 14 15 16 17 18 19 20 nc nc dc dc nc nc nc cs nc nc gnd vcc nc nc soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd nc nc cs sck si so nc nc nc nc nc nc nc vcc nc nc wp reset rdy/busy nc nc nc nc nc nc nc nc cbga top view through package a b c d e 1 2345 nc nc nc nc nc vcc wp reset nc nc gnd rdy/bsy si nc nc sck cs so nc nc nc nc nc nc note: plcc package pins 16 and 17 are don ? t connect
AT45DB161 2 while a page in the main memory is being reprogrammed. unlike conventional flash memories that are accessed ran- domly with multiple address lines and a parallel interface, the dataflash uses a serial interface to sequentially access its data. the simple serial interface facilitates hardware lay- out, increases system reliability, minimizes switching noise, and reduces package size and active pin count. the device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. typical applications for the dataflash are digital voice storage, image storage, and data storage. the device operates at clock frequencies up to 13 mhz with a typical active read current consumption of 4ma. to allow for simple in-system reprogrammability, the AT45DB161 does not require high-input voltages for pro- gramming. the device operates from a single power supply, 2.7v to 3.6v, for both the program and read opera- tions. the AT45DB161 is enabled through the chip select pin (cs ) and accessed via a three-wire interface consisting of the serial input (si), serial output (so), and the serial clock (sck). all programming cycles are self-timed, and no separate erase cycle is required before programming. block diagram memory array to provide optimal flexibility, the memory array of the AT45DB161 is divided into three levels of granularity com- prising of sectors, blocks, and pages. the memory architecture diagram illustrates the breakdown of each level and details the number of pages per sector and block. all program operations to the dataflash occur on a page by page basis; however, the optional erase operations can be performed at the block or page level. flash memory array page (528 bytes) buffer 2 (528 bytes) buffer 1 (528 bytes) i/o interface sck cs reset vcc gnd rdy/busy wp so si
AT45DB161 3 memory architecture diagram device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in table 1 and table 2. a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. while the cs pin is low, toggling the sck pin controls the loading of the opcode and the desired buffer or main memory address location through the si (serial input) pin. all instructions, addresses, and data are transferred with the most significant bit (msb) first. read by specifying the appropriate opcode, data can be read from the main memory or from either one of the two data buffers. main memory page read: a main memory read allows the user to read data directly from any one of the 4096 pages in the main memory, bypassing both of the data buff- ers and leaving the contents of the buffers unchanged. to start a page read, the 8-bit opcode, 52h, is followed by 24 address bits and 32 don ? t care bits. in the AT45DB161, the first two address bits are reserved for larger density devices (see notes on page 10), the next 12 address bits (pa11-pa0) specify the page address, and the next 10 address bits (ba9-ba0) specify the starting byte address within the page. the 32 don ? t care bits which follow the 24 address bits are sent to initialize the read operation. fol- lowing the 32 don ? t care bits, additional pulses on sck result in serial data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bits, and the reading of data. when the end of a page in main memory is reached during a main memory page read, the device will continue reading at the beginning of the same page. a low-to-high transition on the cs pin will terminate the read operation and tri-state the so pin. buffer read: data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. an opcode of 54h is used to read data from buffer 1, and an opcode of 56h is used to read data from buffer 2. to perform a buffer read, the eight bits of the opcode must be followed by 14 don ? t care bits, 10 address bits, and eight don ? t care bits. since the buffer size is 528 bytes, 10 address bits (bfa9-bfa0) are required to specify the first byte of data to be read from the buffer. the cs pin must remain low during the loading of the opcode, the address bits, the don ? t care bits, and the reading of data. when the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. a low- to-high transition on the cs pin will terminate the read operation and tri-state the so pin. sector = 135,168 bytes (128k + 4k) 32 blocks (256 pages) sector 0 sector 1 sector 2 sector 3 sector 4 sector 5 sector 6 sector 7 sector 8 sector 9 sector 10 sector 11 sector 12 sector 13 sector 14 sector 15 block = 4224 bytes (4k + 128) 8 pages block 0 block 1 block 30 block 31 block 32 block 33 block 510 block 511 sector 0 block 62 block 63 block 64 block 65 block 66 block 509 sector 1 page = 528 bytes (512 + 16) page 0 page 1 page 6 page 7 page 8 page 9 page 4094 page 4095 block 0 page 14 page 15 page 16 page 17 page 18 page 4093 block 1 sector architecture block architecture page architecture
AT45DB161 4 main memory page to buffer transfer: a page of data can be transferred from the main memory to either buffer 1 or buffer 2. an 8-bit opcode, 53h for buffer 1 and 55h for buffer 2, is followed by the two reserved bits, 12 address bits (pa11-pa0) which specify the page in main memory that is to be transferred, and 10 don ? t care bits. the cs pin must be low while toggling the sck pin to load the opcode, the address bits, and the don ? t care bits from the si pin. the transfer of the page of data from the main memory to the buffer will begin when the cs pin transitions from a low to a high state. during the transfer of a page of data (t xfr ), the status register can be read to determine whether the transfer has been completed or not. main memory page to buffer compare: a page of data in main memory can be compared to the data in buffer 1 or buffer 2. an 8-bit opcode, 60h for buffer 1 and 61h for buffer 2, is followed by 24 address bits consisting of the two reserved bits, 12 address bits (pa11-pa0) which specify the page in the main memory that is to be com- pared to the buffer, and 10 don ? t care bits. the loading of the opcode and the address bits is the same as described previously. the cs pin must be low while toggling the sck pin to load the opcode, the address bits, and the don ? t care bits from the si pin. on the low-to-high transition of the cs pin, the 528 bytes in the selected main memory page will be compared with the 528 bytes in buffer 1 or buffer 2. dur- ing this time (t xfr ), the status register will indicate that the part is busy. on completion of the compare operation, bit 6 of the status register is updated with the result of the compare. program buffer write: data can be shifted in from the si pin into either buffer 1 or buffer 2. to load data into either buffer, an 8-bit opcode, 84h for buffer 1 or 87h for buffer 2, is followed by 14 don ? t care bits and 10 address bits (bfa9- bfa0). the 10 address bits specify the first byte in the buffer to be written. the data is entered following the address bits. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low-to- high transition is detected on the cs pin. buffer to main memory page program with built-in erase: data written into either buffer 1 or buffer 2 can be programmed into the main memory. an 8-bit opcode, 83h for buffer 1 or 86h for buffer 2, is followed by the two reserved bits, 12 address bits (pa11-pa0) that specify the page in the main memory to be written, and 10 additional don ? t care bits. when a low-to-high transition occurs on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the programming of the page are internally self-timed and should take place in a maxi- mum time of t ep . during this time, the status register will indicate that the part is busy. buffer to main memory page program with- out built-in erase: a previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. an 8-bit opcode, 88h for buffer 1 or 89h for buffer 2, is followed by the two reserved bits, 12 address bits (pa11-pa0) that specify the page in the main memory to be written, and 10 additional don ? t care bits. when a low-to-high transition occurs on the cs pin, the part will program the data stored in the buffer into the spec- ified page in the main memory. it is necessary that the page in main memory that is being programmed has been previously erased. the programming of the page is inter- nally self-timed and should take place in a maximum time of t p . during this time, the status register will indicate that the part is busy. page erase: the optional page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program without built-in erase command to be utilized at a later time. to perform a page erase, an opcode of 81h must be loaded into the device, followed by two reserved bits, 12 address bits (pa11-pa0), and 10 don ? t care bits. the 12 address bits are used to specify which page of the memory array is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected page to 1s. the erase operation is internally self-timed and should take place in a maximum time of t pe . during this time, the status register will indicate that the part is busy. block erase: a block of eight pages can be erased at one time allowing the buffer to main memory page pro- gram without built-in erase command to be utilized to reduce programming times when writing large amounts of data to the device. to perform a block erase, an opcode of 50h must be loaded into the device, followed by two reserved bits, nine address bits (pa11-pa3), and 13 don ? t care bits. the nine address bits are used to specify which block of eight pages is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected block of eight pages to 1s. the erase operation is internally self-timed and should take place in a maximum time of t be . during this time, the status register will indicate that the part is busy.
AT45DB161 5 main memory page program: this operation is a combination of the buffer write and buffer to main memory page program with built-in erase operations. data is first shifted into buffer 1 or buffer 2 from the si pin and then pro- grammed into a specified page in the main memory. an 8-bit opcode, 82h for buffer 1 or 85h for buffer 2, is fol- lowed by the two reserved bits and 22 address bits. the 12 most significant address bits (pa11-pa0) select the page in the main memory where data is to be written, and the next 10 address bits (bfa9-bfa0) select the first byte in the buffer to be written. after all address bits are shifted in, the part will take data from the si pin and store it in one of the data buffers. if the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. when there is a low-to-high transition on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the program- ming of the page are internally self-timed and should take place in a maximum of time t ep . during this time, the status register will indicate that the part is busy. auto page rewrite: this mode is only needed if multi- ple bytes within a page or multiple pages of data are modified in a random fashion. this mode is a combination of two operations: main memory page to buffer transfer and buffer to main memory page program with built-in erase. a page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its origi- nal page of main memory. an 8-bit opcode, 58h for buffer 1 or 59h for buffer 2, is followed by the two reserved bits, 12 address bits (pa11-pa0) that specify the page in main memory to be rewritten, and 10 additional don ? t care bits. when a low-to-high transition occurs on the cs pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. if a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in figure 1 on page 17 is recommended. otherwise, if multi- ple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in figure 2 on page 18 is recommended. status register: the status register can be used to determine the device ? s ready/busy status, the result of a main memory page to buffer compare operation, or the device density. to read the status register, an opcode of 57h must be loaded into the device. after the last bit of the opcode is shifted in, the eight bits of the status register, starting with the msb (bit 7), will be shifted out on the so pin during the next eight clock cycles. the five most signifi- cant bits of the status register will contain device information, while the remaining three least significant bits are reserved for future use and will have undefined values. after bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as cs remains low and sck is being toggled) starting again with bit 7. the data in the status register is constantly updated, so each repeating sequence will output new data. ready/busy status is indicated using bit 7 of the status reg- ister. if bit 7 is a 1, then the device is not busy and is ready to accept the next command. if bit 7 is a 0, then the device is in a busy state. the user can continuously poll bit 7 of the status register by stopping sck once bit 7 has been output. the status of bit 7 will continue to be output on the so pin, and once the device is no longer busy, the state of so will change from 0 to 1. there are eight operations which can block erase addressing pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 block 000000000xxx0 000000001xxx1 000000010xxx2 000000011xxx3 111111100xxx508 111111101xxx509 111111110xxx510 111111111xxx511
AT45DB161 6 cause the device to be in a busy state: main memory page to buffer transfer, main memory page to buffer compare, buffer to main memory page program with built-in erase, buffer to main memory page program without built-in erase, page erase, block erase, main memory page pro- gram, and auto page rewrite. the result of the most recent main memory page to buffer compare operation is indicated using bit 6 of the status register. if bit 6 is a 0, then the data in the main memory page matches the data in the buffer. if bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. the device density is indicated using bits 5, 4, and 3 of the status register. for the AT45DB161, the three bits are 1, 0, and 1. the decimal value of these three binary bits does not equate to the device density; the three bits represent a combinational code relating to differing densities of serial dataflash devices, allowing a total of eight different density configurations. read/program mode summary the modes listed above can be separated into two groups ? modes which make use of the flash memory array (group a) and modes which do not make use of the flash memory array (group b). group a modes consist of: 1. main memory page read 2. main memory page to buffer 1 (or 2) transfer 3. main memory page to buffer 1 (or 2) compare 4. buffer 1 (or 2) to main memory page program with built-in erase 5. buffer 1 (or 2) to main memory page program without built-in erase 6. page erase 7. block erase 8. main memory page program 9. auto page rewrite group b modes consist of: 1. buffer 1 (or 2) read 2. buffer 1 (or 2) write 3. status register read if a group a mode is in progress (not fully completed) then another mode in group a should not be started. however, during this time in which a group a mode is in progress, modes in group b can be started. this gives the serial dataflash the ability to virtually accommodate a continuous data stream. while data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). see application note an-4 ( ? using atmel ? s serial dataflash ? ) for more details. hardware page write protect: if the wp pin is held low, the first 256 pages of the main memory cannot be reprogrammed. the only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. the wp pin is internally pulled high; therefore, connection of the wp pin is not necessary if this pin and feature will not be utilized. however, it is recommended that the wp pin be driven high externally whenever possible. reset : a low state on the reset pin (reset ) will terminate the operation in progress and reset the internal state machine to an idle state. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on reset circuit, so there are no restrictions on the reset pin during power-on sequences. the reset pin is also internally pulled high; therefore, connection of the reset pin is not necessary if this pin and feature will not be utilized. how- ever, it is recommended that the reset pin be driven high externally whenever possible. ready/busy : this open drain output pin will be driven low when the device is busy in an internally self-timed oper- ation. this pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during program- ming operations, compare operations, and during page-to- buffer transfers. the busy status indicates that the flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. power-on/reset state when power is first applied to the device, or when recover- ing from a reset condition, the device will default to spi mode 3. in addition, the so pin will be in a high-impedance state, and a high-to-low transition on the cs pin will be required to start a valid instruction. the spi mode will be automatically selected on every falling edge of cs by sam- pling the inactive clock state. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/busy comp101xxx
AT45DB161 7 note: 1. after power is applied and v cc is at the minimum specified datasheet value, the system should wait 20 ms before an opera- tional mode is started. absolute maximum ratings* temperature under bias ................................ -55 c to +125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v dc and ac operating range AT45DB161 operating temperature (case) com. 0 c to 70 c ind. -40 c to 85 c v cc power supply (1) 2.7v to 3.6v
AT45DB161 8 dc characteristics symbol parameter condition min typ max units i sb standby current cs , reset , wp = v ih , all inputs at cmos levels 310a i cc1 active current, read operation f = 13 mhz; i out = 0 ma; v cc = 3.6v 4 10 ma i cc2 active current, program/erase operation v cc = 3.6v 15 35 ma i li input load current v in = cmos levels 1 a i lo output leakage current v i/o = cmos levels 1 a v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v ac characteristics symbol parameter min typ max units f sck sck frequency 13 mhz t wh sck high time 35 ns t wl sck low time 35 ns t cs minimum cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns t csb cs high to rdy/busy low 200 ns t su data in setup time 10 ns t h data in hold time 20 ns t ho output hold time 0 ns t dis output disable time 25 ns t v output valid 30 ns t xfr page to buffer transfer/compare time 250 350 s t ep page erase and programming time 10 20 ms t p page programming time 715ms t pe page erase time 610ms t be block erase time 715ms t rst reset pulse width 10 s t rec reset recovery time 1s input test waveforms and measurement levels t r , t f < 5 ns (10% to 90%) ac driving levels ac measurement level 0.45v 2.0 0.8 2.4v output test load device under test 30 pf
AT45DB161 9 ac waveforms two different timing diagrams are shown below. waveform 1 shows the sck signal being low when cs makes a high- to-low transition, and waveform 2 shows the sck signal being high when cs makes a high-to-low transition. both waveforms show valid timing diagrams. the setup and hold times for the si signal are referenced to the low-to-high transition on the sck signal. waveform 1 shows timing that is also compatible with spi mode 0, and waveform 2 shows timing that is compatible with spi mode 3 waveform 1 ? inactive clock polarity low waveform 2 ? inactive clock polarity high cs sck si so tcss valid in th tsu twh twl tcsh tcs tv high impedance valid out tho tdis high impedance cs sck si so tcss valid in th tsu twl twh tcsh tcs tv high z valid out tho tdis high impedance
AT45DB161 10 reset timing (inactive clock polarity low shown) command sequence for read/write operations (except status register read) notes: 1. ? r ? designates bits reserved for larger densities. 2. it is recommended that ? r ? be a logical ? 0 ? for densities of 16m bits or smaller. 3. for densities larger than 16m bits, the ? r ? bits become the most significant page address bit for the appropriate density. cs sck reset so si trst trec tcss high impedance high impedance si cmd 8 bits 8 bits 8 bits msb reserved for larger densities page address (pa11-pa0) byte/buffer address (ba9-ba0/bfa9-bfa0) lsb r r x x x x x x x x x x x x x x x x x x x x x x
AT45DB161 11 write operations the following block diagram and waveforms illustrate the various write sequences available. main memory page program through buffers buffer write buffer to main memory page program (data from buffer programmed into flash page) flash memory array page (528 bytes) buffer 2 (528 bytes) buffer 1 (528 bytes) i/o interface si buffer 1 to main memory page program main memory page program through buffer 2 buffer 2 to main memory page program main memory page program through buffer 1 buffer 1 write buffer 2 write si cmd n n+1 last byte completes writing into selected buffer starts self-timed erase/program operation cs r r , pa11-6 pa5-0, bfa9-8 bfa7-0 si cmd x x x, bfa9-8 bfa7-0 n n+1 last byte completes writing into selected buffer cs si cmd pa5-0, xx x cs starts self-timed erase/program operation r r , pa11-6 n = 1st byte written n+1 = 2nd byte written each transition represents 8 bits and 8 clock c y cles
AT45DB161 12 read operations the following block diagram and waveforms illustrate the various read sequences available. main memory page read main memory page to buffer transfer (data from flash page read into buffer) buffer read flash memory array page (528 bytes) buffer 2 (528 bytes) buffer 1 (528 bytes) i/o interface main memory page to buffer 1 main memory page to buffer 2 main memory page read buffer 1 read buffer 2 read so si cmd pa5-0, ba9-8 ba7-0 x xxx cs n n+1 so r r , pa11-6 si cmd pa5-0, xx x starts reading page data into buffer cs so r r , pa11-6 si cmd x x x, bfa9-8 bfa7-0 cs n n+1 so x n = 1st byte read n+1 = 2nd byte read each transition represents 8 bits and 8 clock c y cles
AT45DB161 13 detailed bit-level read timing ? inactive clock polarity low main memory page read buffer read status register read si 0 1 0 10 xxx cs so sck 12345 60 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb tsu tv si 0 1 0 10 xxx cs so sck 12345 36 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb tsu tv si 0 1 0 10 111 cs so sck 12345 78910 11 12 16 17 high-impedance d 7 d 6 d 5 status register output command opcode msb tsu tv 6 d 1 d 0 d 7 lsb msb
AT45DB161 14 detailed bit-level read timing ? inactive clock polarity high main memory page read buffer read status register read si 0 1 0 10 xxx cs so sck 12345 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb tsu tv d 4 68 si 0 1 0 10 xxx cs so sck 12345 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb tsu tv d 4 44 si 0 1 0 10 111 cs so sck 12345 78910 11 12 17 18 high-impedance d 7 d 6 d 5 status register output command opcode msb tsu tv 6 d 4 d 0 d 7 lsb msb d 6
AT45DB161 15 table 1. main memory page read buffer 1 read buffer 2 read main memory page to buffer 1 transfer main memory page to buffer 2 transfer main memory page to buffer 1 compare main memory page to buffer 2 compare buffer 1 write buffer 2 write opcode 52h 54h 56h 53h 55h 60h 61h 84h 87h 000000011 111111100 000001100 111110000 000000000 011010011 101100001 000110101 rxxrrrrxx rxxrrrrxx pa 1 1 x x pa 1 1 pa 1 1 pa 1 1 pa 1 1 x x pa 1 0 x x pa 1 0 pa 1 0 pa 1 0 pa 1 0 x x pa 9 x x pa 9 pa 9 pa 9 pa 9 x x pa 8 x x pa 8 pa 8 pa 8 pa 8 x x pa 7 x x pa 7 pa 7 pa 7 pa 7 x x pa 6 x x pa 6 pa 6 pa 6 pa 6 x x pa 5 x x pa 5 pa 5 pa 5 pa 5 x x pa 4 x x pa 4 pa 4 pa 4 pa 4 x x pa 3 x x pa 3 pa 3 pa 3 pa 3 x x pa 2 x x pa 2 pa 2 pa 2 pa 2 x x pa 1 x x pa 1 pa 1 pa 1 pa 1 x x pa 0 x x pa 0 pa 0 pa 0 pa 0 x x ba9bfa9bfa9xxxxbfa9bfa9 ba8bfa8bfa8xxxxbfa8bfa8 ba7bfa7bfa7xxxxbfa7bfa7 ba6bfa6bfa6xxxxbfa6bfa6 ba5bfa5bfa5xxxxbfa5bfa5 ba4bfa4bfa4xxxxbfa4bfa4 ba3bfa3bfa3xxxxbfa3bfa3 ba2bfa2bfa2xxxxbfa2bfa2 ba1bfa1bfa1xxxxbfa1bfa1 ba0bfa0bfa0xxxxbfa0bfa0 xxx x (don ? t care) r (reserved bits) xxx xxx xxx xxx xxx xxx xxx x (64th bit)
AT45DB161 16 table 2. buffer 1 to main memory page program with built-in erase buffer 2 to main memory page program with built-in erase buffer 1 to main memory page program without built-in erase buffer 2 to main memory page program without built-in erase page erase block erase main memory page program through buffer 1 main memory page program through buffer 2 auto page rewrite through buffer 1 auto page rewrite through buffer 2 status register opcode 83h 86h 88h 89h 81h 50h 82h 85h 58h 59h 57h 1 1 1 1 1011000 0 0 0 0 0100111 0 0 0 0 0000000 0 0 0 0 0100111 0 0 1 1 0000110 0 1 0 0 0001001 1 1 0 0 0010001 1 0 0 1 1001011 r r r r rrrrrr r r r r rrrrrr pa11 pa11 pa11 pa11 pa11 pa11 pa11 pa11 pa11 pa11 pa10 pa10 pa10 pa10 pa10 pa10 pa10 pa10 pa10 pa10 pa9 pa9 pa9 pa9 pa9 pa9 pa9 pa9 pa9 pa9 pa8 pa8 pa8 pa8 pa8 pa8 pa8 pa8 pa8 pa8 pa7 pa7 pa7 pa7 pa7 pa7 pa7 pa7 pa7 pa7 pa6 pa6 pa6 pa6 pa6 pa6 pa6 pa6 pa6 pa6 pa5 pa5 pa5 pa5 pa5 pa5 pa5 pa5 pa5 pa5 pa4 pa4 pa4 pa4 pa4 pa4 pa4 pa4 pa4 pa4 pa3 pa3 pa3 pa3 pa3 pa3 pa3 pa3 pa3 pa3 pa2 pa2 pa2 pa2 pa2 x pa2 pa2 pa2 pa2 pa1 pa1 pa1 pa1 pa1 x pa1 pa1 pa1 pa1 pa0 pa0 pa0 pa0 pa0 x pa0 pa0 pa0 pa0 x x x x x x bfa9 bfa9 x x x x x x x x bfa8 bfa8 x x x x x x x x bfa7 bfa7 x x x x x x x x bfa6 bfa6 x x x x x x x x bfa5 bfa5 x x x x x x x x bfa4 bfa4 x x x x x x x x bfa3 bfa3 x x x x x x x x bfa2 bfa2 x x x x x x x x bfa1 bfa1 x x x x x x x x bfa0 bfa0 x x x (don ? t care) r (reserved bits)
AT45DB161 17 figure 1. algorithm for sequentially programming or reprogramming an entire sector notes: 1. this type of algorithm is used for applications in which an entire sector is programmed sequentially, filling the secto r page- by-page. 2. a page can be written using either a main memory page program operation or a buffer write operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire sector. start main memory page program (82h, 85h) end provide address and data buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
AT45DB161 18 figure 2. algorithm for randomly modifying data notes: 1. to preserve data integrity, each page of a dataflash sector (256 pages per sector) must be updated/rewritten at least o nce within every 10,000 cumulative page erase/program operations within that sector. 2. a page address pointer must be maintained to indicate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer. 3. other algorithms can be used to rewrite portions of the flash array. low power applications may choose to wait until 10,000 cumulative page erase/program operations have accumulated before rewriting all 256 pages of the sector. see application note an-4 ( ? using atmel ? s serial dataflash ? ) for more details. sector addressing pa11 pa10 pa9 pa8 sector 0000 0 0001 1 0010 2 1101 13 1110 14 1111 15 start main memory page to buffer transfer (53h, 55h) increment page address pointer (2) auto page rewrite (2) (58h, 59h) end provide address of page to modify if planning to modify multiple bytes currently stored within a page of the flash array main memory page program (82h, 85h) buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
AT45DB161 19 package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 28r 28-lead, 0.330" wide, plastic gull wing small outline (soic) 28t 28-lead, plastic thin small outline package (tsop) 24c2 24-ball, 5 x 5 array plastic chip-scale ball grid array (cbga) ordering information f sck (mhz) i cc (ma) ordering code package operation range active standby 13 10 0.01 AT45DB161-jc AT45DB161-rc AT45DB161-tc AT45DB161-cc 32j 28r 28t 24c2 commercial (0 c to 70 c) 13 10 0.01 AT45DB161-ji AT45DB161-ri AT45DB161-ti AT45DB161-ci 32j 28r 28t 24c2 industrial (-40 c to 85 c)
AT45DB161 20 packaging information 24c2, 24-ball (5 x 5 array), 1.0 mm pitch, 7 x 9.5 mm plastic chip-scale ball grid array (cbga) dimensions in millimeters and (inches)* *controlling dimension: millimeters a b c d e 5432 4.0 (0.157) 2.87 (0.113) 2.61 (0.103) 0.46 (0.018) dia ball typ 1.62 (0.064) 1.36 (0.054) 4.0 (0.157) 7.2 (0.283) 6.8 (0.268) 1.40 (0.055) max 0.30 (0.012) 9.7 (0.381) 9.3 (0.366) 1.00 (0,039) bsc non-accumulative 1 32j , 32-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-016 ae .045(1.14) x 45? pin no. 1 identify .025(.635) x 30? - 45? .012(.305) .008(.203) .021(.533) .013(.330) .530(13.5) .490(12.4) .030(.762) .015(.381) .095(2.41) .060(1.52) .140(3.56) .120(3.05) .032(.813) .026(.660) .050(1.27) typ .553(14.0) .547(13.9) .595(15.1) .585(14.9) .300(7.62) ref .430(10.9) .390(9.90) at contact points .022(.559) x 45? max (3x) .453(11.5) .447(11.4) .495(12.6) .485(12.3) 28r , 28-lead, 0.330" wide, plastic gull wing small outline (soic) dimensions in inches and (millimeters) 28t , 28-lead, plastic thin small outline package (tsop) dimensions in millimeters and (inches)* *controlling dimension: millimeters index mark area 0.55 (0.022) bsc 0.20 (0.008) 0.10 (0.004) 7.15 (0.281) ref 8.10 (0.319) 7.90 (0.311) 1.25 (0.049) 1.05 (0.041) 0.27 (0.011) 0.18 (0.007) 11.9 (0.469) 11.7 (0.461) 13.7 (0.539) 13.1 (0.516) 0 5 0.20 (0.008) 0.15 (0.006) ref 0.70 (0.028) 0.30 (0.012)
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